Logic Design Using FPGAs (CME 341.0)

Recent/Current Offerings

Syllabus / Public content Section Term Instructor
CME 341 01 September 2017 Joseph Salt
CME 341 L01 September 2017 Joseph Salt
CME 341 01 September 2016 Joseph Salt
CME 341 L01 September 2016 Joseph Salt


This course investigates techniques for designing large digital circuits with the Verilog Hardware Description Language (Verilog HDL). The course focuses on FPGAs; however, the techniques discussed are also applicable to the design of ASICs. The architectures of FPGAs are discussed in general with certain aspects of their internal operation discussed in detail. Emphasis is placed on connecting the Verilog HDL code to the hardware circuit that is constructed by the Verilog compiler and router.


EE 431


CMPT 116 and EE 232.


Students with credit for EE 431 will not receive credit for this course.

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